ICT2014 Abstracts

Site-specific active cooling using low-dimensionality thermoelectric (TE) devices has become a very promising, cost-effective, environmentally safe and portable cooling solution with potential applications in high-performance integrated circuits. These modern chips have specific areas of high heat fluxes causing hot spots that limit the chip’s reliability and performance. Recently, integration/embedding of Bi₂Te₃ superlattice based thin-film thermoelectric coolers into state-of-the-art electronic packages has been experimentally demonstrated and active cooling of as much as 15 ºC at the hot spot on a silicon chip with a high heat flux (~1,300 Wcm^-2) has been reported [1]. In this work, our objective is to develop a multiscale and modular simulator for TE coolers, where the material and device parameters are obtained atomistically using molecular dynamics simulations and then used in the system level design and optimization. After benchmarking the simulator against the above mentioned experimental results, we then carry out a detailed numerical investigation of the performance of Bi₂Te₃ nanowire based thermoelectric devices for hot-spot cooling. The results suggest that active hotspot cooling of as high as 20 ºC with larger heat flux (compared to the thin-film counterparts) is achievable using such low-dimensionality structures. However, it has been observed that thermal and electrical contact resistances, which are gigantic in nanostructures, play a critical role in determining the cooling range and lead to significant performance degradation that must be addressed before these devices can be deployed in such applications.

*Supported by National Science Foundation Grant No. CCF-1218839

[1] I. Chowdhury et al., “On-chip cooling by superlattice-based thin-film thermoelectrics,” Nature Nanotechnology 4, 235–238 (2009).